The Very Large Integrated Systems (VLSI) Research Group at the University of Minnesota focuses on developing core circuit technologies for enabling smart and energy-efficient integrated systems. Applications we target range from machine learning and neuromorphic computing, hardware security, internet-of-things, medical devices, sensor networks, radiation hardened chips, to beyond CMOS computing. Our group’s research frequently appears in top VLSI technology and circuit design publications such as ISSCC, IEDM, VLSI, CICC, IRPS, NSREC, and various IEEE journals.
Sep. 2015: Prof. Kim is promoted to full professor.
June 2015: Good luck to students going for summer internships: Jongyeon (HGST), Won Ho (IBM), Qianying (IBM), Saurabh (Intel), and Somnath (Rambus and Intel).
May 2015: Our group will present three papers at the 2015 VLSI Technology and Circuits Symposium on topics ranging from bang-bang digital PLL, AC electromigration, and spintronics based analog-to-digital conversion.
Dec. 2014: Our group published a paper in the Proceedings of the IEEE on the history, current status, and future challenges of spintronics technology. [LINK]
Sep. 2013: Prof. Kim's article about the future of VLSI technology featured in the Circuit Cellar magazine. [PAPER]
Jul. 2013: The 32nm adaptive PLL chip designed by Bongjin and Weichao has been selected as a winning entry for the 2013 ISLPED low power design contest. Congratulations!
Apr. 2013: Writeback-free Embedded DRAM designed by former students Wei Zhang and Ki Chul Chun appears in an online news article [ARTICLE]
Feb. 2013: Our group participates in the newly formed Center for Spintronics Materials, Interfaces, and Novel Architectures (C-SPIN), a $28 million grant from DARPA, U.S. semiconductor companies, and defense industry. [Press release]
Jan. 2013: Three papers from our group have been accepted for publication in the 2013 International Reliability Physics Symposium (IRPS).
Sep. 2012: Our joint paper with Prof. J.P. Wang's group on Spin-Torque Transfer Magnetic RAMs (STT-MRAMs) was accepted for publication in the IEEE Journal of Solid-State Circuits (JSSC). Thanks Ki Chul for leading this effort!
Sep. 2012: Wei Zhang presented his eDRAM paper at the Custom Integrated Circuits Conference (CICC) [PAPER][SLIDES]. Ayan Paul gave a presentation at SRC techcon on his multi-core power delivery work [PAPER][SLIDES].
Aug. 2012: Pulkit Jain's paper on SRAM reliability monitoring was accepted for publication in the 2012 International Electron Devices Meeting (IEDM). Congratulations!
June 2012: Congratulations to Seung-hwan and Ki Chul for being selected as a winning entry for the ISLPED student design contest. The title of their design is "An Embedded Flash Memory in a Generic 65nm Logic Process for Zero-Standby-Power System-on-Chip Applications".
Apr. 2012: Prof. Kim gave an invited talk on flexible electronics design at the Design of Medical Devices Conference. [SLIDES]
Jan. 2012: Our eDRAM paper was published in JSSC. [PAPER]
Nov. 2011: Our statistical odometer paper was published in JSSC. [PAPER]
May. 2011: IEEE Spectrum Magazine publishes our silicon odometer work in the May 2011 hardcopy issue. [Article]
Mar. 2011: MIT Technology Review covers our printed flexible organic memory research. [URL]