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Pusan (2011) B. Kim, W. Xu, C.H. Kim, "A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter ", VLSI Circuits Symposium, Jun. 2013 |
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Ipanema (2010) P. Jain, A. Paul, X. Wang, C.H. Kim, "A 32nm SRAM Reliability Macro for Recovery Free Evaluation of NBTI and PBTI ", International Electron Devices Meeting (IEDM), Dec. 2012 [SLIDES] |
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Budapest (2010) · W. Zhang, K.C. Chun, C.H. Kim, "A Write-Back-Free 2T1D Embedded DRAM with Local Voltage Sensing and a Dual-Row-Access Low Power Mode", Custom Integrated Circuits Conference (CICC), Sep. 2012 [PAPER][SLIDES] · [ISLPED International Low Power Design Contest Winner]S. Song, K.C. Chun, C.H. Kim, "A Logic-Compatible Embedded Flash Memory Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme", VLSI Circuits Symposium, Jun. 2012 [PAPER][SLIDES] · S. Song, K. Chun, C. H. Kim, "A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme", IEEE Journal of Solid-State Circuits (JSSC), May 2013 [PAPER] · A. Paul, M. Amrein, S. Gupta, A. Vinod, A. Arun, S. Sapatnekar, C.H. Kim, "Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Issues in Multi-core Multi-power Domain Processors", Custom Integrated Circuits Conference (CICC), Sep. 2012 [PAPER][SLIDES] · P. Jain, J. Keane, C.H. Kim, "An Array-Based Chip Lifetime Predictor Macro for Gate Dielectric Failures in Core and IO FETs", European Solid-State Device Research Conference (ESSDERC), Sep. 2012 [PAPER][SLIDES] |
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3DIC (2009) · P. Jain, D. Jiao, X. Wang, C.H. Kim, "Measurement, Analysis and Improvement of Supply Noise in 3D ICs", VLSI Circuits Symposium, Jun. 2011 [PAPER][SLIDES] |
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Beagle (2009) · K. Chun, W. Zhang, P. Jain, C.H. Kim, "A 700 MHz 2T1C Embedded DRAM Macro in a Generic Logic Process with No Boosted Supplies", International Solid-State Circuits Conference (ISSCC), Feb. 2011 [PAPER][SLIDES] · D. Jiao and C.H. Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise", International Solid-State Circuits Conference (ISSCC), Feb. 2011 [PAPER][SLIDES] |
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Euka (2009) · J. Keane, W. Zhang, C.H. Kim, "An On-Chip Monitor for Statistically Significant Circuit Aging Characterization", International Electron Devices Meeting (IEDM), Dec. 2010 [PAPER][SLIDES] · K. Chun, P. Jain, T. Kim, C.H. Kim, "A 1.1V, 667MHz Random Cycle, Asymmetric 2T Gain Cell Embedded DRAM with a 99.9 Percentile Retention Time of 110µsec", VLSI Circuits Symposium, June 2010 [PAPER] [SLIDES] |
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Toro (2008) · [Appeared in IEEE Spectrum Magazine] J. Keane, D. Persaud, and C.H. Kim, "An All-in-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB", VLSI Circuits Symposium, June 2009 [PAPER] [SLIDES] [Online article] · [ISLPED International Low Power Design Contest Winner] K. Chun, P. Jain, J. Lee, C.H. Kim, "A Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell, Regulated Bit-line Write Scheme and PVT-tracking Read Reference Bias", VLSI Circuits Symposium, June 2009 [PAPER] [SLIDES] · D. Jiao, J. Gu, C.H. Kim, "Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise", Custom Integrated Circuits Conference (CICC), Sep. 2009 [PAPER] [SLIDES] · T. Kim, W. Zhang, C.H. Kim, "An SRAM Reliability Test Macro for Fully-Automated Statistical Measurements of Vmin Degradation", Custom Integrated Circuits Conference (CICC), Sep. 2009 [PAPER] [SLIDES] |
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Hiyoko (2008) |
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Kenny (2007) · J. Keane, S. Venkatraman, P. Butzen, and C.H. Kim, "An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization", Custom Integrated Circuits Conference (CICC), Sep. 2008 [PAPER] [SLIDES] · T. Kim, J. Liu, and C.H. Kim, "A Voltage Scalable 0.26V, 64kb 8T SRAM with VminLowering Techniques and Deep Sleep Mode", Custom Integrated Circuits Conference (CICC), Sep. 2008 [PAPER] [SLIDES] |
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Kyle (2007) · T. Kim, R. Persaud, and C.H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", VLSI Circuits Symposium, June 2007 [PAPER] [SLIDES] · T. Kim, R. Persaud, and C.H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits, Apr. 2008 [PAPER] |
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Cartman (2006) · T. Kim, J. Liu, J. Keane, and C.H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", International Solid-State Circuits Conference (ISSCC), Feb 2007 [PAPER] [SLIDES] · J. Gu, H. Eom, and C.H. Kim, "A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping", VLSI Circuits Symposium, June 2007 [PAPER] [SLIDES] · J. Keane, T. Kim, and C.H. Kim, "An On-chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007 [PAPER] |