• Reliability Aware Aging Tolerant Design

Device reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Time Dependent Dielectric Breakdown (TDDB) have emerged as serious problems undermining the performance and yield of VLSI systems in advanced CMOS technologies. ITRS recognizes these reliability issues as major roadblocks for continuing CMOS scaling beyond the 32nm technology node. Circuit aging manifests itself as degradation in chip performance over time. The time it takes for a chip to show significant slow down from its fresh state can be in the order of a few months to a few years depending on the operating conditions. Circuit aging has been an unfamiliar notion to chip designers until recent where the heat dissipation, operating voltage margins, and manufacturing variability has become unacceptable in high-performance systems. To effectively deal with this adverse phenomenon, my group has been developing innovative design-for-reliability techniques that make chips inherently resilient to aging or equip chips with intelligent measures to adaptively compensate for aging. Most of the previous research on this topic has been confined to understanding the aging behavior of a single transistor. As a result, the impact of aging on higher-level circuits and systems has not been well understood and there has virtually been no work on design-for-reliability techniques to resolve this adverse phenomenon. As we have experienced with other artifacts of Moore's law, technology is now reaching a point where device reliability can no longer be dealt with at the device level alone. Our vision is to embrace a new design paradigm where the circuit aging issues are handled at every single stage of the design starting from the process development to circuit design and system architecture. Check out the following IEEE Spectrum article for more details on our groups research activity on this topic [click here]

  • Robust Low Voltage Memory Design (SRAM, DRAM, MRAM, OTP)

Memory has always been and always will be a critical building block for virtually all integrated circuit applications. Design of memory circuits is challenging comparing to other datapath circuits due to the small transistor dimensions which have worse process fluctuations and the low noise margin at sub-1V supplies. The inter-chip process variations, coupled with the intrinsic intra-chip variations in threshold voltage can result in failure of a memory cells. In particular, a memory cell failure can occur due to unstable read/write operations, failure in the data holding capability of the cell at standby mode, or an increase in the cell access.
My team has developed and implemented circuit techniques for several different types of memories. Our work started with designing Static Random Access Memories (SRAMs) that can operate at a wide range of supply voltage from the super-threshold region to the sub-threshold region. A voltage scalable 0.60V to 0.26V, 64kb 8T SRAM in a 130nm CMOS was built with a marginal bitline leakage compensation technique and a deep sleep mode. Our innovative design was recognized by a Samsung Humantech thesis award. Embedded DRAMs (eDRAMs) are a potent competitor against mainstream SRAMs in sub-1V due to their cell size advantage and non-ratioed circuit operation. Design challenges for eDRAMs are drastically different from those of SRAMs, since their operation is similar to a DRAM, though they are greatly constrained by being built in a logic process rather than a memory-specific process. Under the presence of high leakage and process variations, it is a major challenge to robustly build eDRAM designs that can ensure practical refresh times of at least few hundred microseconds, so that they can be effectively used in large caches.
In collaboration with the Magnetic Device Group led by Prof. Jianping Wang's team in the ECE department, we have also been implementing a Spin-Torque Transfer Random Access Memory (STTRAM) with record low write power. Spin-torque transfer theory, originally proposed in 1996, has the potential to overcome the fundamental limitations encountered in traditional field-based magnetic RAMs such as large write current, large device dimensions, half-select problem, and poor reliability.

  • Circuit/Architecture/Device Co-Optimization for Nanoscale VLSI Systems

Scaling has made a transistor virtually free in terms of cost and area. Designers have more freedom than ever to integrate complex functions in a single package under given power constraint. However, optimizing one building block for power and performance may not yield optimal results in others. As a simple example, datapath units prefer a low Vdd and low Vt for low dynamic power whereas memory elements require a higher Vdd and higher Vt to maintain functionality and suppress leakage. Accordingly, a discrepancy exists in the direction of optimization within a single integrated system. I would like to explore device, circuit and architecture solutions to achieve the best performance and power in future integrated systems consisting of heterogeneous components with different design roadmaps.

  • Organic TFT Circuit and System Design

Organic thin-film-transistor (OTFT) is a class of exploratory device that we are currently investigating in collaboration with Prof. Daniel Frisbie in the chemical engineering department at the University of Minnesota. OTFTs are drawing much attention as it has attributes such as structural flexibility, low temperature processing, large area coverage and low cost which make them attractive for large-area electronics. Various forms of OTFTs can either enable applications that were not achievable using traditional mainstream inorganic TFTs, or far surpass them in terms of performance and cost. Flexible display panels, electronic paper, large-area sensors, and sheet type scanners are some of the new applications enabled by OTFT technology. Although OTFT technology has reached a point where initial commercial applications can be considered, the lack of a systematic design methodology has been impeding further progress in building complex OTFT systems that can fully exploit this emerging technology. The overarching goal of this project is to develop a comprehensive design framework from a designer's viewpoint for the efficient design of OTFT integrated circuits. Since embarking on this project in 2007, we have built physics-based compact models that agree well with OTFT measurement data and have designed OTFT-specific digital circuits using the models. A proposal has been recently submitted to NSF.