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- U. Karpuzcu, H. Cılasun, W. Moy, Z. Zeng, T. Islam, H. Lo, A. Vanasse, M. Tan, M. Anees, Ramprasath S, A. Kumar, S. Sapatnekar, and C.H. Kim, "COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization", April 2024 [PREPRINT V1]
- H. Cılasun, Z. Zeng, Ramprasath S, A. Kumar, H. Lo, W. Cho, W. Moy, C.H. Kim, U. Karpuzcu, and S. Sapatnekar, “3SAT on an all‑to‑all‑connected CMOS Ising solver chip”, Scientific Reports, 2024 [PAPER]
- Y. Hong, M. Kim, and C.H. Kim, “NAND Flash based Neural Network Accelerator”, TinyML, Best Prototype Award, 2024 [LINKEDIN POST]
- [Best Student Paper] Y. Yi, A. Kteya, A. Volkov, S. Moreau, V. Sukharev, and C.H. Kim, “Electromigration Test Chip Experiments From Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis”, International Reliability Physics Symposium (IRPS), 2024 [PAPER] [SLIDES]
- H. Lo, W. Moy, H. Yu, S. Sapatnekar, and C.H. Kim, “An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture”, Nature Electronics [IEEE SPECTRUM] [ANNOUNCEMENT] [COVER IMAGE] [ARTICLE]
- H. Cılasun, Z. Zeng, Ramprasath S, A. Kumar, H. Lo, W. Cho, C.H. Kim, U. Karpuzcu, S. Sapatnekar, “3SAT on an All-to-All-Connected CMOS Ising Solver Chip” (arXiv) https://arxiv.org/abs/2309.11017
- H. Lo, W. Moy, H. Yu, S. Sapatnekar, and C.H. Kim, “A 48-node All-to-all Connected Coupled Ring Oscillator Ising Solver Chip” (preprint) https://doi.org/10.21203/rs.3.rs-2395566/v1
- A. Kteyan, V. Sukharev, A. Volkov, J. Choy, F. Najm, Y. Yi, C.H. Kim, and S. Moreau, “Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution”, International Symposium on Physical Design (ISPD), 2023 [PAPER]
- Y. Yi, C. Zhou, A. Kteyan, V. Sukharev and C.H. Kim, “Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters”, International Reliability Physics Symposium (IRPS), 2023 [PAPER]
- H. Yu, Y. Yi, N. Pande, and C.H. Kim, “On-chip Heater Design and Control Methodology for Reliability Testing Applications Requiring over 300°C Local Temperatures”, IEEE Trans. Device and Material Reliability (TDMR), 2023 [PAPER]
- Chris Kim and William Moy, "Quantum Computing without Quantum Computers", Nature Research Briefing, 2022 [LINK]
- W. Moy, I. Ahmed, P. Chiu, J. Moy, S. Sapatnekar and C.H. Kim, "A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving", Nature Electronics, 2022 [NATURE] [PAPER]
- V. Sukharev, A. Kteyan, J. Choy, F. N. Najm, Y. Yi, C.H. Kim, “Experimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids”, Design Automation Conference (DAC), 2022
- T. Islam, J. Kim, D. Tipple, M. Nelson, R. Jin, A. Jarrar, and C.H. Kim, "A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal", International Reliability Physics Symposium (IRPS), 2022 [PAPER] github.com/reliability-research/odometer
- N. Pande, C. Zhou, MH Lin, R. Fung, R. Wong, S. Wen, and C.H. Kim, “A 16nm All-digital Hardware Monitor for Evaluating Electromigration effects in Signal Interconnects through Bit-Error-Rate Tracking”, IEEE Trans. on Device and Materials Reliability, 2022 [PAPER]
- P. Chiu and C.H. Kim, “A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors”, IEEE Trans. on Circuits and Systems I, 2022 [PAPER]
- M. Kim, M. Liu, L. Everson, and C.H. Kim, “An Embedded NAND Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process”, IEEE Journal of Solid-State Circuits (JSSC), Feb. 2022 [PAPER]
- [Invited] A. Kteyan, V. Sukharev, and C.H. Kim, "Novel Methodology for Temperature-Aware Electromigration Assessment in On-chip Power Grid: Simulations and Experimental Validation", International Reliability Physics Symposium (IRPS), 2022
- V. Sukharev, A. Kteyan, F. Najm, Y. Yi, C.H. Kim, J. Choy, S. Torosyan, and Y. Zhu, "Experimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2021 [IEEExplore]
- N. Pande, S. Kumar, L. Everson, G. Park, I. Ahmed and C.H. Kim, "Neutron-Induced Pulse Width Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain Based Test Structure", IEEE Trans. on Nuclear Science, 2021 [PAPER]
- S. Kumar, M. Cho, L. Everson, A. Malavasi, D. Lake, C. Tokunaga, M. Khellah, J. Tschanz, V. De, and C.H. Kim, "A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses", IEEE Trans. on VLSI Systems, 2021 [PAPER]
- [Invited] C. Kim, "Coupled Oscillator based Computing: Using Nature to Solve Difficult Problems", IBM Unconventional Computing Paradigm Workshop, 2021 [SLIDES]
- K. Khatamifard, Z. Chowdhury, N. Pande, M. Razaviyayn, C.H. Kim, and U. Karpuzcu, “GeNVoM: Read Mapping Near Non-Volatile Memory”, IEEE/ACM Trans. on Computational Biology and Bioinformatics, 2021 [PAPER]
- Y. Yi and C.H. Kim, “Circuit-based Power-grid Electromigration Monitoring Test Vehicle”, SRC Techon, Sep. 2021
- H. Yu and C.H. Kim, “Array-based Device Characterization Under Extreme Temperature”, SRC Techon, Sep. 2021
- H. Yu*, G. Park*, and C.H. Kim, "Extreme Temperature Characterization of Amplifier Response Up to 300 Degrees Celsius Using Integrated Heaters and On-Chip Samplers", European Solid-State Circuits Conference (ESSCIRC), 2021, *equal contribution [PAPER][SLIDES]
- [Invited] C. Kim, "3D NAND Flash Ready Neural Networks: Learnings and Afterthoughts", NSF In-Memory Computing Workshop, 2021 [SLIDES]
- [Invited] C. Kim, "Coupled Oscillator based Computing: Using Nature to Solve Difficult Problems", IEEE Custom Integrated Circuits Conference (CICC), Education Session, 2021 [SLIDES]
- N. Pande, C. Zhou, M.H. Lin, R. Fung, R. Wong, S. Wen, and C.H. Kim, “Electromigration-Induced Bit-Error-Rate Degradation of Interconnect Signal Paths Characterized from a 16nm Test Chip”, VLSI Technology Symposium, 2021 [PAPER][SLIDES]
- I. Ahmed, P. Chiu, W. Moy, and C.H. Kim, “A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems”, IEEE Journal of Solid-State Circuits (JSSC), 2021 [PAPER]
- S. Vangal, S. Paul, S. Hsu, Am. Agarwal, S. Kumar, R. Krishnamurthy, H. Krishnamurthy, J. Tschanz, V. De, and C.H. Kim, “Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities”, IEEE Trans. on VLSI Systems (TVLSI), 2021 [PAPER]
- L. Everson, S. Sapatnekar, and C.H. Kim, “A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control”, IEEE Journal of Solid-State Circuits (JSSC), 2021 [PAPER]
- G. Park, M. Kim, and C.H. Kim, "An All BTI (PMOS NBTI, PMOS PBTI, NMOS NBTI, NMOS PBTI) Odometer based on a Dual Power Rail Ring Oscillator Array", International Reliability Physics Symposium (IRPS), Mar. 2021 [PAPER][SLIDES]
- [Invited] C.H. Kim, “Circuit based Characterization of Signal Line and Power Grid Electromigration Effects”, Microelectronics Reliability and Qualification Workshop (MRQW), Feb. 2021
- "Guest Editor: Special Topic on Coupled Oscillators for Non-von Neumann Computation", IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Dec. 2020 [LINK]
- [Invited] J. Song, JP Wang, and C.H. Kim, “MRAM DTCO and Compact Models”, International Electron Devices Meeting (IEDM), Dec. 2020 [SLIDES]
- Y. Yi, N. Pande, and C.H. Kim, “Circuit-based Approaches Towards Characterizing Electromigration Effects in Signal Interconnects and Power Grids”, SRC Techcon, Sep. 2020
- [Invited] C. Kim, “Characterization and Mitigation of Electromigration Effects in Advanced Nodes”, International Interconnect Technology Conference (IITC), Oct. 2020
- J. Song, H. Dixit, B Behin-Aein, C.H. Kim, and W. Taylor, "Impact of Process Variability on Write Error Rate and Read Disturbance in STT-MRAM Devices", IEEE Trans. on Magnetics, 2020 [PAPER]
- I. Ahmed, P. Chiu, and C.H. Kim, "A Probabilistic Self-annealing Compute Fabric based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems", Symposia on VLSI Technology and Circuits, June 2020 [PAPER] [SLIDES] Watch video here
- L. Everson, J. Song, and C.H. Kim, “A Shortest Path Finding Time-based Accelerator Core with Built-in Gravity Control and Buffer Zone for Smooth 3D Navigation”, IEEE Solid-State Circuits Letters, 2020 [PAPER]
- N. Pande, S. Kumar, L. Everson, G. Park, I. Ahmed and C.H. Kim, “Neutron-Induced Pulse Width Distribution of Logic Gates Characterized Using a Pulse Shrinking Chain Based Test Structure”, IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2020
- M. Kim, J. Song and C.H. Kim, “Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1uA Current Steps”, International Reliability Physics Symposium (IRPS), Mar. 2020 [PAPER]
- P. Chiu and C.H. Kim, “A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel Loss Monitor”, International Solid-State Circuits Conference (ISSCC), Feb. 2020 [PAPER] [SLIDES]
- N. Pande, S. Kumar, L. Everson, C.H. Kim, "Understanding the Key Parameter Dependences Influencing the Soft-Error Susceptibility of Standard Combinational Logic", IEEE Trans. on Nuclear Science, 2019 [PAPER]
- C. Zhou, R. Fung, S. Wen, R. Wong, and C.H. Kim, "Electromigration Effects in Power Grids Characterized from a 65 nm Test Chip", IEEE Trans. On Device and Materials Reliabiltiy (TDMR), 2019 [PAPER]
- M. Kim, M. Liu, L. Everson, G. Park, Y. Jeon, S. Kim, S. Lee, S. Song, and C.H. Kim, “A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process”, IEEE International Electron Devices Meeting (IEDM), Dec. 2019 [PAPER] [SLIDES]
- N. Pande, C. Zhou, MH Lin, R. Fung, R. Wong, S. Wen, and C.H. Kim, “Characterizing Electromigration Effects in a 16nm FinFET Process Using a Circuit Based Test Vehicle”, IEEE International Electron Devices Meeting (IEDM), Dec. 2019 [PAPER] [SLIDES]
- [Invited] M. Kim, G. Park, P. Chiu, and C.H. Kim, “Leveraging Circuit Reliabilty Effects for Designing Robust and Secure Physical Unclonable Functions”, IEEE International Electron Devices Meeting (IEDM), Dec. 2019 [PAPER] [SLIDES]
- [Invited] C.H. Kim, “Circuit based Characterization of Power Grid and Interconnect Electromigration Effects”, International Conference on Reliability and Stress-related Phenomena in Nano and Microelectronics (IRSP), Nov. 2019
- N. Pande, S. Kumar, L. Everson, and C.H. Kim, “Understanding the Key Parameter Dependencies Influencing the Soft-Error Susceptibility of Standard Combinational Logic”, IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2019
- [Invited] L. Everson, M. Liu, and C.H. Kim, “An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65nm”, IEEE Journal of Solid-State Circuits [PAPER]
- L. G. Rocha, M. Liu, D. Biswas, B. Verhoef, S. Bampi, C.H. Kim, C. Van Hoof, M. Verhelst, N. Van Helleputte, M. Konijnenburg, “Real-Time HR Estimation from Wrist PPG Using Binary LSTMs”, IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2019
- L. Everson, D. Biswas, B. Verhoef, C.H. Kim, C. Van Hoof, M. Konijnenburg, N. Van Helleputte, “BioTranslator: Inferring R-Peaks from Ambulatory Wrist-Worn PPG Signal”, Engineering in Medicine and Biology Conference (EMBC), July 2019
- D. Biswas, N. Simoes, L. Everson, C.H. Kim, C. Hoof, M. Konijnenburg, N. Van Helleputte, “Heart Rate Estimation From Wrist-Worn Photoplethysmography Sensors: A Systematic Review”, IEEE Engineering in Medicine and Biology Conference (EMBC), May 2019
- N. Pande, S. Kumar, L. Everson, and C.H. Kim, “Understanding the Key Parameter Dependencies Influencing the Soft-Error Susceptibility of Standard Combinational Logic”, IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2019
- M. Liu and C.H. Kim, “A Powerless and Non-volatile Counterfeit IC Detection Sensor in Standard Logic Processes Based on an Exposed Floating-Gate Array”, IEEE Trans. on Electron Devices (TED), Issue 6, Vol. 66, pp. 2735-2740, June 2019 [PAPER]
- S. Kumar, M. Cho, L. Everson, Q. Tang, P. Meinerzhagen, A. Malavasi, D. Lake, C. Tokunaga, M. Khellah, J. Tschanz, V. De, and C.H. Kim, “Analysis of Neutron-Induced Multi-Bit-Upset (MBU) Clusters in 14nm Tri-Gate Flip-Flop Array”, IEEE Trans. on Nuclear Science (TNS), Apr. 2019 [PAPER]
- G. Park, M. Kim, N. Pande, P. Chiu, J. Song and C.H. Kim, “A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing”, Custom Integrated Circuits Conference (CICC), Apr. 2019 [PAPER] [SLIDES]
- N. Pande, G. Park, S. Krishnan, V. Reddy, and C.H. Kim, “Investigating the Aging Dynamics of Diode-connected MOS Devices using an Array-based Characterization Vehicle in a 65nm Process”, International Reliability Physics Symposium (IRPS), Mar. 2019 [PAPER] [SLIDES]
- L. Everson, S. Sapatnekar, and C.H. Kim, “A 40x40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2-Dimensional Gradient Control”, International Solid-State Circuits Conference (ISSCC), Feb. 2019 [PAPER] [SLIDES]
- D. Biswas, L. Everson, M. Liu, M. Panwar, B. Verhoef, S. Patrika, C.H. Kim, A. Acharyya, C. Van Hoof, N. Van Helleputte, "CorNET: Deep Learning framework for PPG based Heart Rate Estimation and Biometric Identification in Ambulant Environment", IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), Jan. 2019 [PAPER]
- J. Song, I. Ahmed, Z. Zhao, D. Zhang, S. Sapatnekar, J. Wang, and C.H. Kim, “Evaluation of Operating Margin and Switching Probability of Voltage Controlled Magnetic Anisotropy (VCMA) Magnetic Tunnel Junctions”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JxCDC), Dec. 2018 [PAPER]
- M. Kim, J. Kim, G. Park, L. Everson, H. Kim, S. Song, S. Lee, C.H. Kim, “A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology”, International Electron Devices Meeting (IEDM), Dec. 2018 [PAPER] [SLIDES]
- L. Everson, M. Liu, N. Pande, and C.H. Kim, “A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm”, IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018 [PAPER] [SLIDES]
- P. Chiu, M. Liu, Q. Tang, and C.H. Kim, “A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer”, IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2018 [PAPER] [SLIDES]
- [Invited] S. Kundu, M. Liu, S. Wen, R. Wong, and C.H. Kim, “A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer”, IEEE Journal of Solid-State Circuits (JSSC), Jan. 2019 [PAPER]
- L. Everson, S. Kundu, G. Chen, Z. Yang, T. Ebner, C.H. Kim, “A 0.0094mm2/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording”, IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2018 [PAPER] [SLIDES]
- J. Song, C.H. Kim, “Potential and Challenge of Voltage-Controlled Magnetic Anisotropy (VCMA) MTJ Devices for Nonvolatile Memory Applications”, SRC Techcon, Sep. 2018
- G. Park, N. Pande, V. Reddy, C.H. Kim, “Understanding the aging dynamics in Analog/Mixed-Signal circuits through simple on-chip monitoring and representative test structures”, SRC Techcon, Sep. 2018
- C. Zhou, R. Wong, S. Wen, and C.H. Kim, “Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping Points”, VLSI Technology Symposium, June 2018 [PAPER] [SLIDES]
- S. Kumar, M. Cho, L. Everson, Q. Tang, P. Mazanec, P. Meinerzhagen, A. Malavasi, D. Lake, C. Tokunaga, M. Khellah, J. Tschanz, S. Borkar, V. De, and C.H. Kim, “Analyzing Neutron-Induced Multi-Bit-Upset (MBU) Patterns in 14nm Tri-Gate Flip-Flop Array”, Nuclear and Space Radiation Effects Conference (NSREC), July 2018
- [Best paper candidate] R. Zand, K. Camsari, S. Pyle, I. Ahmed, C.H. Kim, R. Demara, “Low-Energy Deep Belief Networks using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons”, Great Lakes Symposium on VLSI (GLSVLSI), May 2018
- R. Zand, K. Camsari, I. Ahmed, S. Pyle, C.H. Kim, S. Datta, and R. DeMara, “R-DBN: A Resistive Deep Belief Network Architecture Leveraging the Intrinsic Behavior of Probabilistic Devices” [LINK]
- Q. Tang, W. Choi, L. Everson, K. Parhi, and C.H. Kim, “A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC”, International Symposium on Circuits and Systems (ISCAS), May 2018 [PAPER] [SLIDES]
- A. Koyily, C.H. Kim, K. Parhi, “Predicting Soft-Response of MUX PUFs via Logistic Regression of Total Delay Difference”, International Symposium on Circuits and Systems (ISCAS), May 2018
- L. Everson, D. Biswas, M. Panwar, C.H. Kim, C. Van Hoof, M. Konijnenburg, N. Van Helleputte, “DeepNet based Biometric Identification using Wrist-Worn PPG in Ambulatory Environment” International Symposium on Circuits and Systems (ISCAS), May 2018
- [Best student paper candidate] G. Park, B. Kim, M. Kim, V. Reddy, and C. H. Kim, “All-Digital PLL Frequency and Phase Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits”, International Reliability Physics Symposium (IRPS), Mar. 2018 [PAPER] [SLIDES]
- [Invited] P. Chiu, S. Kundu, Q. Tang, and C.H. Kim, “A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer”, IEEE Journal of Solid-State Circuits (JSSC) [PAPER]
- S. Kundu, M. Liu, S. Wen, R. Wong, and C.H. Kim, “A Fully Integrated 40pF Output Capacitor Beat-frequency Quantizer based Digital LDO with Built-in Adaptive Sampling and Active Voltage Positioning”, International Solid-State Circuits Conference (ISSCC), Feb. 2018 [PAPER] [SLIDES]
- A. Koyily, S.V.S. Avvaru, C. Zhou, C.H. Kim and K. K. Parhi, "Effect of Aging on Linear and Nonlinear MUX PUFs by Statistical Modeling," Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2018 [PAPER]
- C. Zhou, X. Wang, R. Fung, S. Wen, R. Wong, and C.H. Kim, "A Circuit based Approach for Characterizing High Frequency Electromigration Effects," IEEE Trans. on Device and Materials Reliability (TDMR), 2018 [PAPER]
- I Ahmed, Z. Zhao, M. Mankalale, S. Sapatnekar, J.P. Wang, C.H. Kim, “A Comparative Study between Spin-Transfer-Torque (STT) and Spin-Hall-Effect (SHE) Switching Mechanisms using SPICE”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2018 [PAPER]
- S. Koeteshwara, C.H. Kim, K. Parhi, “Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design”, IEEE Trans. on Information Forensics and Security (TIFS), 2018 [PAPER]
- [Best Student Paper Candidate] S. Kumar, M. Cho, L. Everson, H. Kim, Q. Tang, P. Mazanec, P. Meinerzhagen, A. Malavasi , D. Lake, C. Tokunaga, M. Khellah, J. Tschanz, S. Borkar, V. De and C.H. Kim, “An Ultra-Dense Irradiation Test Structure with a NAND/NOR Readout Chain for Characterizing Soft Error Rates of 14nm Combinational Logic Circuits”, International Electron Devices Meeting (IEDM), Dec. 2017 [PAPER] [SLIDES]
- S. Koteshwara, C.H. Kim, and K. Parhi, “Functional Encryption fo Integrated Circuits by Key-Based Dynamical Obfuscation”, Asilomar Conference, Nov. 2017
- C. Zhou, K. Parhi, and C.H. Kim, “Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements”, SRC Techcon, Sep. 2017
- J.P. Wang, S. Sapatnekar, C.H. Kim, et al., “INVITED: A Pathway to Enable Exponential Scalign for the Beyond-CMOS Era”, Design Automation Conference (DAC), June 2017
- S. Avvuru, C. Zhou, C.H. Kim, and K. Parhi, “Predicting Hard and Soft-Responses and Identifying Stable Challenges of MUX PUFs using ANNs”, IEEE Midwest Sympoisum on Circuits and Systems, Boston, MA, Aug. 2017
- W. Rojas, J. McMorrow, M. Geier, Q. Tang, C.H. Kim, T. Marks, and M. Hersam, "Solution-Processed Carbon Nanotube True Random Number Generator", Nano Letters, July 2017 [PAPER]
- Q. Tang and C. H. Kim, “Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit”, IEEE Journal of Solid-State Circuits (JSSC), Apr. 2017 [PAPER]
- [Best Paper Award] M. Liu, C. Zhou, K. Parhi, and C.H. Kim, "A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2017 [PAPER] [SLIDES]
- M. Mankalale, Z. Liang, J. Zhao, C.H. Kim, J.P. Wang, and S. Sapatnekar, “CoMET: Composite-Input Magnetoelectric-based Logic Technology”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), Apr. 2017
- S. Kumar, L. Everson, I. Ahmed, M. Liu, Q. Tang, H. Quinn, M. Cho, M. Khellah, J. Tschanz, S. Borkar, V. De, and C.H. Kim, “A Circuit Technique for Characterizing Single-Event-Transient Pulses”, Nuclear and Space Radiation Effects Conference (NSREC), July 2017 (to appear)
- P. Chiu, S. Kundu, Q. Tang, and C.H. Kim, “A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer”, VLSI Circuits Symposium, June 2017 [PAPER] [SLIDES]
- S. Kumar, M. Cho, L. Everson, H. Kim, Q. Tang, P. Mazanec, P. Meinerzhagen, A. Malavasi, D. Lake, C. Tokunaga, H. Quinn, M. Khellah, J. Tschanz, S. Borkar, V. De, and C.H. Kim, “Statistical Characterization of Radiation-Induced Pulse Waveforms and Flip-Flop Soft Errors in 14nm Tri-Gate CMOS Using a Back-Sampling Chain (BSC) Technique”, VLSI Circuits Symposium, June 2017 [PAPER] [SLIDES]
- M. Liu and C.H. Kim, “A Powerless and Non-volatile Counterfeit IC Detection Sensor in a Standard Logic Process Based on an Exposed Floating-Gate Array”, VLSI Technology Symposium, June 2017 [PAPER] [SLIDES]
- S. Kundu and C.H. Kim, “A Multi-Phase VCO Quantizer Based Adaptive Digital LDO in 65nm CMOS Technology”, International Symposium on Circuits and Systems (ISCAS), May 2017 [PAPER] [SLIDES]
- A. Koyily, C. Zhou, C.H. Kim, and K. Parhi, “An Entropy Test for Determining Whether a Mux PUF Is Linear or Nonlinear”, International Symposium on Circuits and Systems (ISCAS), May 2017
- S. Koteshwara, C.H. Kim, and K. Parhi, “Hierarchical Functional Obfuscation of Integrated Circuits Using a Mode-Based Approach”, International Symposium on Circuits and Systems (ISCAS), May 2017
- [Best Paper Candidate] C. Zhou, K. Parhi, and C.H. Kim, “Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements”, Design Automation Conference (DAC), June 2017 [PAPER] [SLIDES]
- Q. Tang, C. Zhou, W. Choi, G. Kang, J. Park, K. Parhi, and C.H. Kim, “A DRAM based Physical Unclonable Function Capable of Generating >1032 Challenge Response Pair per 1Kbit Array for Secure Chip Authentication”, Custom Integrated Circuits Conference (CICC), Apr. 2017 [PAPER] [SLIDES]
- M. Liu, L. Everson, and C.H. Kim, “A Scalable Time-based Integrate-and-Fire Neuromorphic Core with Leak and Local Lateral Inhibition Capabilities”, Custom Integrated Circuits Conference (CICC), Apr. 2017 [PAPER] [SLIDES]
- Q. Tang, S. Kumar, D. Fulkerson, and C.H. Kim, “A Compact High-Sensitivity 2-Transistor Radiation Sensor Array”, International Reliability Physics Symposium (IRPS), Apr. 2017 [PAPER]
- S. Kundu, B. Kim, C.H. Kim, “A 0.2-to-1.45GHz Subsampling Fractional-N Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Static Phase Offset Detection”, IEEE Journal of Solid-State Circuits (JSSC), 2017 [PAPER]
- A. Paul, S. Park, D. Somasekhar, Y. Kim, N. Borkar, U. Karpuzcu, and C.H. Kim, "System-level Power Analysis of a Multi-core Multi-power Domain Processor with On-chip Voltage Regulators", IEEE Trans. on VLSI Systems (TVLSI), Dec. 2016 [PAPER]
- C. Kshirsagar, W. Xu, Y. Su, M. Robbins, C.H. Kim, and S.J. Koester, "Dynamic Memory Cells Using MoS Field-Effect Transistors Demonstrating Femtoampere Leakage Currents ", ACS Nano, Aug. 2016 [PAPER]
- Y. Lao, Q. Tang, C.H. Kim, and K. Parhi, "Beat Frequency Detector based High-Speed True Random Number Generators: Statistical Modeling and Analysis", ACM Journal on Emerging Technologies in Computing Systems (JETC), May 2016
- S. Kundu and C.H. Kim, "A 0.0054mm2 Frequency-to-Current Conversion Based Fractional Frequency Synthesizer in 32nm SOI Utilizing Deep Trench Capacitor", IEEE Trans. Circuits and Systems II (TCAS2), May 2016 [PAPER]
- Q. Tang and C.H. Kim, "Assessing the Impact of RTN on Logic Timing Failures Using a 32nm Dual Ring Oscillator Array Based Test Structure", SRC Techcon, Sep. 2016
- [Best paper award] C. Zhou, S. Satapathy, Y. Lao, K. Parhi, and C.H. Kim, "Soft Response Generation and Thresholding Strategies for Linear and Feedforward MUX based PUFs", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2016 [PAPER][SLIDES]
- W. Choi, Y. Lv, J. Kim, H. Kim, A. Deshpande, G. Kang, J.P. Wang, and C.H. Kim, "Random Number Generation and Analog-to-Digital Conversion Based on a Magnetic Tunnel Junction", Non Volatile Memories (NVM) Workshop, Mar. 2016
- S. Avvaru, C. Zhou, S. Satapathy, Y. Lao, C.H. Kim, and K. Parhi, "Estimating Delay Differences of Arbiter PUFs Using Silicon Data", Design Automation and Test in Europe (DATE), Mar. 2016
- S. Kundu, B. Kim, and C.H. Kim, "A 0.2-1.45GHz Sub-sampling Fractional-N All-Digital MDLL with Zero-offset Aperture PD based Spur Cancellation and In-situ Timing Mismatch Detection", International Solid-State Circuits Conference (ISSCC), Feb. 2016 [PAPER][SLIDES]
- S. Koteshwara, C.H. Kim, and K. Parhi, "Mode-based Obfuscation using Control-Flow Modifications", Workshop on Cryptography and Security in Computing Systems (CS2), Jan. 2016
- Q. Tang and C.H. Kim, "Assessing the Impact of RTN on Logic Timing Margin Using a 32nm Dual Ring Oscillator Array", International Electron Devices Meeting (IEDM), Dec. 2015 [PAPER][SLIDES]
- H. Zheng, A. Ramm, S. Lim, W. Xie, B. Ahn, W. Xu, A. Mahajan, W. Suszynski, C.H. Kim, J. Lewis, C.D. Frisbie, and L. Francis, "Wettability Contrast Gravure Printing", Advanced Materials, Oct. 2015 [PAPER]
- M. Geier, J. McMorrow, W. Xu, J. Zhu, C.H. Kim, T.J. Marks, and M.C. Hersam, "Solution-processed carbon nanotube thin-film complementary static random access memory", Nature Nanotechnology (impact factor=34.1), Sep. 2015 [PAPER]
- S. Kundu, B. Kim, and C.H. Kim, "Two-step Beat Frequency Quantizer Based ADC with Adaptive Reference Control for Low Swing Bio-potential Signals", Custom Integrated Circuits Conference (CICC), Sep. 2015 [PAPER][SLIDES]
- [Nominated for best student paper] W. Choi, H. Kim, and C.H. Kim, "Circuit Techniques for Mitigating Short-Term Vth Instability Issues in Successive Approximation Register (SAR) ADCs", Custom Integrated Circuits Conference (CICC), Sep. 2015 [PAPER][SLIDES]
- [Nominated for best student paper] B. Kim, H. Kim, and C.H. Kim, "An 8bit, 2.6ps Two-Step TDC in 65nm CMOS Employing a Switched Ring-Oscillator Based Time Amplifier", Custom Integrated Circuits Conference (CICC), Sep. 2015 [PAPER][SLIDES]
- J. Kim, A. Chen, B. Behin-Aein, S. Kumar, J.P. Wang, and C.H. Kim, "A Technology-Agnostic MTJ SPICE Model with User-Defined Dimensions for STT-MRAM Scalability Studies", Custom Integrated Circuits Conference (CICC), Sep. 2015 [PAPER][SLIDES]
- W. Choi, Y. Lv, J. Kim, H. Kim, A. Deshpande, G. Kang, J.P Wang, and C.H. Kim, "True Random Number Generator and Analog-to-Digital Converter based on a Magnetic Tunnel Junction", SRC Techcon, Sep. 2015
- S. Kundu, V. Kireev, and C.H. Kim, "A 8-14 GHz Varactorless Current Controlled LC Oscillator in 16nm CMOS Technology", IEEE Midwest Symposium on Circuits and Systems (MWCAS), Sep. 2015 [PAPER]
- B. Kim, S. Kundu, and C.H. Kim, "A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit", VLSI Circuits Symposium, Jun. 2015 [PAPER][SLIDES]
- C. Zhou, X. Wang, R. Fung, S. Wen, R. Wong, and C.H. Kim, "High Frequency AC Electromigration Lifetime Measurements from a 32nm Test Chip", VLSI Technology Symposium, Jun. 2015 [PAPER][SLIDES]
- [Nominated for best student paper] W. Choi, Y. Lv, H. Kim, J.P. Wang, and C.H. Kim, "An 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching Probability of a Magnetic Tunnel Junction", VLSI Technology Symposium, Jun. 2015 [PAPER][SLIDES]
- J. Kim, W. Tuohy, C. Ma, W. Choi, I. Ahmed, D. Lilja, and C.H. Kim, "Spin-Hall Effect MRAM Based Cache Memory: A Feasibility Study", Device Research Conference (DRC), Jun. 2015 [PAPER][SLIDES]
- W. Choi, J. Kim, I. Ahmed, and C.H. Kim, "A Comprehensive Study on Interface Perpendicular MTJ Variability", Device Research Conference (DRC), Jun. 2015 [PAPER][SLIDES]
- [High school student paper] R. Parhi, C.H. Kim, and K. Parhi, "Fault-Tolerant Ripple-Carry Binary Adder Using Partial Triple Modular Redundancy (PTMR)", International Symposium on Circuits and Systems (ISCAS), May 2015 [PAPER]
- S. Satapathy, W. Choi, X. Wang, and C.H. Kim, "A Revolving Reference Odometer Circuit for BTI-Induced Frequency Fluctuation Measurements under Fast DVFS Transients", International Reliability Physics Symposium (IRPS), Apr. 2015 [PAPER][SLIDES]
- X. Wang, Q. Tang, P. Jain, D. Jiao, and C.H. Kim, "The Dependence of BTI and HCI Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications", IEEE Transactions on VLSI Systems, Feb. 2015 [PAPER]
- J. Kim, A. Paul, P.A. Crowell, S.J. Koester, S.S. Sapatnekar, J.P. Wang, C.H. Kim, "Spin Based Computing: Device Concepts, Current Status, and a Case Study on a High Performance Microprocessor", Proceedings of the IEEE, Jan. 2015 [PAPER]
- [Invited] S. Song, K. Chun, C. H. Kim, "A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications", IEEE Journal of Solid-State Circuits (JSSC), Aug. 2014 [PAPER]
- W. Choi, Y. Lv, J. Kim, A. Deshpande, G. Kang, J.P. Wang, C.H. Kim, "A Magnetic Tunnel Junction Based True Random Number Generator with Conditional Perturb and Real-Time Output Probability Tracking", International Electron Devices Meeting (IEDM), Dec. 2014 [PAPER][SLIDES]
- X. Wang, J. Keane, T.H. Kim, Q. Tang, C.H. Kim, "Silicon Odometers: Compact In-situ Aging Sensors for Robust System Design", IEEE Micro, Dec. 2014 [PAPER]
- D. Jariwala, V. Sangwan, J. Seo, W. Xu, J. Smith, C.H. Kim, L. Lauhon, T. Marks, M. Hersam, "Large-Area, Low-Voltage, Antiambipoar Heterojunctions from Solution-Processed Semiconductors", Nano Letters, Dec. 2014 [PAPER]
- S. Song, J. Kim, C. H. Kim, "A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic ", IEEE Trans. on Electron Devices, Nov. 2014 [PAPER]
- Q. Tang, B. Kim, Y. Lao, K.K. Parhi, C.H. Kim, "True Random Number Generator Circuits Based on Single- and Multi-Phase Beat Frequency Detection", Custom Integrated Circuits Conference (CICC), Sep. 2014 [PAPER][SLIDES]
- B. Kim, S. Kundu, S. Ko, and C.H. Kim, "A VCO-based ADC Employing a Multi-Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals", Custom Integrated Circuits Conference (CICC), Sep. 2014 [PAPER][SLIDES]
- W. Choi, S. Satapathy, J. Keane, and C.H. Kim, "A Test Circuit Based on a Ring Oscillator Array for Statistical Characterization of Plasma-Induced Damage", Custom Integrated Circuits Conference (CICC), Sep. 2014 [PAPER][SLIDES]
- X. Wang, W. Xu, and C.H. Kim, "SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging Data", Custom Integrated Circuits Conference (CICC), Sep. 2014 [PAPER][SLIDES]
- J. Kim, H. Zhao, Y. Jiang, A. Klemm, J.P. Wang, and C.H. Kim, "Scaling Analysis of In-plane and Perpendicular Anisotropy MTJs Using a Physics-Based Model", SRC Techon, Sep. 2014
- J. Kim, H. Zhao, Y. Jiang, A. Klemm, J.P. Wang, and C.H. Kim, "Scaling Analysis of In-plane and Perpendicular Anisotropy Magnetic Tunnel Junctions Using a Physics-Based Model"", Device Research Conference (DRC), Jun. 2014 [PAPER]
- C. Kshirsagar, W. Xu, C.H. Kim, and S.J. Koester, "Design and Analysis of MoS2-Based MOSFETs for Ultra-Low-Leakage Dynamic Memory Applications", Device Research Conference (DRC), Jun. 2014 [PAPER]
- C. Zhou, X. Wang, Y. Zhu, V. Janapa Reddi, and C.H. Kim, "Estimation of Instantaneous Frequency Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress-Relaxation Model", International Reliability Physics Symposium (IRPS), Jun. 2014 [PAPER][SLIDES]
- X. Wang, S. Song, A. Paul, and C.H. Kim, "Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit", International Reliability Physics Symposium (IRPS), Jun. 2014 [PAPER][SLIDES]
- B. Del Bel, J. Kim, C.H. Kim, and S. Sapatnekar, "Improving STT-MRAM Density Through Multi-bit Error Correction", Design Automation and Test in Europe (DATE) [PAPER]
- K. Sutaria, J. Velamala, C.H. Kim, T. Sato, and Y. Cao, "Aging Statistics based on Trapping/Detrapping: Compact Modeling and Silicon Validation", IEEE Trans. on Device and Materials Reliability [PAPER]
- [Invited] B. Kim, W. Xu, C.H. Kim, "A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter", IEEE Journal of Solid-State Circuits (JSSC), Apr. 2014 [PAPER]
- S. Koester, C.H. Kim, R. Schrimpf, D. Fleetwood, M. Alles, R. Reed, E. Zhang, "Radiation Effects in 2D Material / High-K Dielectric Interfaces", Government Microcircuit Applications and Critical Technology Conference (GOMACTech), Mar. 2014 [PAPER]
- A. Paul, C. Khsirasgar, S. Sapatnekar, S. Koester, C.H. Kim, "Leakage Modeling for Devices with Steep Sub-thresholdSlope Considering Random Threshold Variations", IEEE VLSI Design Conference, Jan. 2014 [PAPER][SLIDES]
- J. Keane, X. Wang, P. Jain, C.H. Kim, "On-Chip Silicon Odometers for Circuit Aging Characterization", Bias Temperature Instability for Devices and Circuits (Book Chapter), Dec. 2013 [LINK]
- M. Ha, W. Zhang, D. Braga, M. Renn, C.H. Kim, C.D. Frisbie, "Aerosol-Jet-Printed, 1 Volt H-Bridge Drive Circuit on Plastic with Integrated Electrochromic Pixel", ACS Applied Materials and Interfaces, Nov. 2013 [PAPER]
- A. Paul, D. Jiao, S. Sapatnekar, C.H. Kim, "Deep Trench Capacitor based Step-up and Step-down Converters in 32nm CMOS with Bi-directional Current Borrowing and Fast DVFS Capabilities", Asian Solid-State Circuits Conference (ASSCC), Nov. 2013 [PAPER][SLIDES]
- [Invited to JSSC special issue] S. Song, K.C. Chun, C.H. Kim, "A Bit-by-Bit Re-Writable Eflash in a Generic Logic Process for Moderate-Density Embedded Non-Volatile Memory Applications", Custom Integrated Circuits Conference (CICC), Sep. 2013 [PAPER][SLIDES]
- B. Kim, W. Xu, C.H. Kim, "A Fully-Digital Beat-Frequency Based ADC Achieving 37dB SNDR for a 1.6mVpp Input Signal", Custom Integrated Circuits Conference (CICC), Sep. 2013 [PAPER][SLIDES]
- M. Geier, P. Prabhumirashi, J. McMorrow, W. Xu, J. Seo, K. Everaerts, C.H. Kim, T. Marks, M. Hersam, "SubnanowattCarbon Nanotube Complementary Logic Enabled by Threshold Voltage Control", Nano Letters [PAPER]
- P. Zhou, A. Paul, C.H. Kim, S. Sapatnekar, "Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems", IEEE Transactions on VLSI Systems [PAPER]
- [Invited] W. Zhang, K. Chun, and C.H. Kim, "A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode", IEEE Transactions on Circuits and Systems I, Aug. 2013 [PAPER]
- [Nominated for best student paper award] Q. Tang, X. Wang, J. Keane, C. H. Kim, "RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit", VLSI Technology Symposium, Jun. 2013 [PAPER][SLIDES]
- [Invited to JSSC special issue] [ISLPED International Low Power Design Contest Winner] B. Kim, W. Xu, C.H. Kim, "A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter", VLSI Circuits Symposium, Jun. 2013 [PAPER][SLIDES]
- S. Song, K. Chun, C. H. Kim, "A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme", IEEE Journal of Solid-State Circuits (JSSC), May 2013 [PAPER]
- S. Song, J. Kim, C. H. Kim, "Program/Erase Speed, Endurance, Retention, and Disturbance Characteristics of Single-Poly Embedded Flash Cells ", International Reliability Physics Symposium (IRPS), Apr. 2013 [PAPER][SLIDES]
- W. Choi, P. Jain, C. H. Kim, "An Array-Based Circuit for Characterizing Latent Plasma-Induced Damage", International Reliability Physics Symposium (IRPS), Apr. 2013 [PAPER][SLIDES]
- X. Wang, J. Keane, P. Jain, V. Reddy, C. H. Kim, "Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing", International Reliability Physics Symposium (IRPS), Apr. 2013 [PAPER][SLIDES]
- M. Ha, J. Seo, P. Prabhumirashi, W. Zhang, M. Geier, M. Renn, C.H. Kim, M. Hersam, and C.D. Frisbie, "Aerosol Jet Printed, Low Voltage, Electrolyte Gated Carbon Nanotube Ring Oscillators with Sub-5µs Stage Delays", Nano Letters, Feb. 2013 [PAPER]
- K. Chun, H. Zhao, J. D. Harms, T. Kim, J. P. Wang, C. H. Kim, "A Scaling Roadmap and Performance Evaluation of In-plane and Perpendicular MTJ Based STT-MRAMs for High-density Cache Memory", IEEE Journal of Solid-State Circuits (JSSC), Feb. 2013 [PAPER]
- P. Jain, A. Paul, X. Wang, C.H. Kim, "A 32nm SRAM Reliability Macro for Recovery Free Evaluation of NBTI and PBTI ", International Electron Devices Meeting (IEDM), Dec. 2012 [PAPER][SLIDES]
- P. Zhou, W. Choi, B. Kim, C.H. Kim, S. Sapatnekar,"Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications", International Conference on Computer-Aided-Design (ICCAD), Nov. 2012 [PAPER]
- J. Keane, C. H. Kim, Q. Liu, and S. S. Sapatnekar, "Process and Reliability Sensors for Nanoscale CMOS ", IEEE Design & Test Magazine, 2012 [PAPER]
- K. Chun, W. Zhang, P. Jain, C.H. Kim, "A 2T1C Embedded DRAM Macro with No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor", IEEE Journal of Solid-State Circuits (JSSC), Oct. 2012 [PAPER]
- D. Jiao, B. Kim, C.H. Kim, "Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation ", IEEE Journal of Solid-State Circuits (JSSC), Oct. 2012 [PAPER]
- A. Paul, M. Amrein, S. Gupta, A. Vinod, A. Arun, S. Sapatnekar, C.H. Kim, "Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Issues in Multi-core Multi-power Domain Processors", Custom Integrated Circuits Conference (CICC), Sep. 2012 [PAPER][SLIDES]
- W. Zhang, K.C. Chun, C.H. Kim, "A Write-Back-Free 2T1D Embedded DRAM with Local Voltage Sensing and a Dual-Row-Access Low Power Mode", Custom Integrated Circuits Conference (CICC), Sep. 2012 [PAPER][SLIDES]
- P. Jain, J. Keane, C.H. Kim, "An Array-Based Chip Lifetime Predictor Macro for Gate Dielectric Failures in Core and IO FETs", European Solid-State Device Research Conference (ESSDERC), Sep. 2012 [PAPER][SLIDES]
- A. Paul, M. Amrein, S. Gupta, A. Vinod, A. Arun, S. Sapatnekar, C.H. Kim,"Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Issues in Multi-core Multi-power Domain Processors", SRC Techon, Sep. 2012
- [ISLPED International Low Power Design Contest Winner]S. Song, K.C. Chun, C.H. Kim, "A Logic-Compatible Embedded Flash Memory Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme", VLSI Circuits Symposium, Jun. 2012 [PAPER][SLIDES]
- T. Kim, P. Lu, C.H. Kim, "Design of Ring Oscillator Structures for Measuring Isolated NBTI and PBTI", International Symposium on Circuits and Systems (ISCAS), May 2012
- [Invited]C.H. Kim, "Flexible Electronics: Materials, Circuits, and Design Methodology", Design of Medical Devices Conference, Apr. 2012 [SLIDES]
- X. Wang, P. Jain, D. Jiao, C.H. Kim, "Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation", International Reliability Physics Symposium (IRPS), Apr. 2012 [PAPER][SLIDES]
- [Invited]J. Keane, C.H. Kim, "On-Chip Silicon Odometers and their Potential Use in Medical Electronics ", International Reliability Physics Symposium (IRPS), Apr. 2012 [PAPER][SLIDES]
- K. Chun, P. Jain, T. Kim, C.H. Kim, "A 667 MHz Logic-compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-die Caches", IEEE Journal of Solid-State Circuits (JSSC), Feb. 2012 [PAPER]
- J. Keane, W. Zhang, C.H. Kim, "An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization ", IEEE Journal of Solid-State Circuits (JSSC), 2011 [PAPER]
- P. Zhou, D. Jiao, C.H. Kim, S. Sapatnekar, "Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery Network", Custom Integrated Circuits Conference, Sep. 2011 [PAPER]
- D. Jiao, B. Kim, C.H. Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise", SRC Techcon, Sep. 2011
- J. Keane and C.H. Kim, "An Odometer for CPUs", IEEE Spectrum, May 2011 [Article]
- J. Keane, S. Venkatraman, P. Butzen, and C.H. Kim, "An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization", IEEE Trans. on VLSI Systems, May 2011 [PAPER]
- P. Jain, D. Jiao, X. Wang, C.H. Kim, "Measurement, Analysis and Improvement of Supply Noise in 3D ICs", VLSI Circuits Symposium, Jun. 2011 [PAPER][SLIDES]
- J. Kim, B. Linder, R. Rao, T. Kim, P. Lu, K. Jenkins, C.H. Kim, A. Bansal, S. Mukhopadhyay, C.T. Chuang "Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies", International Reliability Physics Sympopsium (IRPS), Apr. 2011 [PAPER]
- S. Kumar, C.H. Kim, S. Sapatnekar, "Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits", IEEE Trans. on VLSI Systems, Apr. 2011 [PAPER]
- C.H. Kim and L. Chang, "Nanoscale Memories Pose Unique Challenges ", IEEE Design and Test Magazine Special Issue, Jan/Feb 2011 [URL]
- K. Chun, W. Zhang, P. Jain, C.H. Kim, "A 700 MHz 2T1C Embedded DRAM Macro in a Generic Logic Process with No Boosted Supplies", International Solid-State Circuits Conference (ISSCC), Feb. 2011 [PAPER][SLIDES]
- D. Jiao and C.H. Kim, "A Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation under Resonant Supply Noise", International Solid-State Circuits Conference (ISSCC), Feb. 2011 [PAPER][SLIDES]
- [Covered by EE times and MIT Technology Review]W. Zhang, M. Ha, D. Braga, M. Renn, C.D. Frisbie, C.H. Kim, "A 1V Printed Organic DRAM Cell Based on Ion-Gel Gated Transistors with a Sub-10nW-per-Cell Refresh Power", International Solid-State Circuits Conference (ISSCC), Feb. 2011 [PAPER][SLIDES][EEtimes][MIT Technology Review]
- K. Chun, P. Jain, J. Lee, C.H. Kim, "A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-die Caches ", IEEE Journal of Solid-State Circuits (JSSC), June 2011 [PAPER]
- J. Keane, W. Zhang, C.H. Kim, "An On-Chip Monitor for Statistically Significant Circuit Aging Characterization", International Electron Devices Meeting (IEDM), Dec. 2010 [PAPER][SLIDES]
- D. Jiao, J. Gu, C.H. Kim, "Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect under Resonant Supply Noise", IEEE Journal of Solid-State Circuits (JSSC), Oct. 2010 [PAPER]
- K. Chun, P. Jain, T. Kim, C.H. Kim, "A 1.1V, 667MHz Random Cycle, Asymmetric 2T Gain Cell Embedded DRAM with a 99.9 Percentile Retention Time of 110µsec", VLSI Circuits Symposium, June 2010 [PAPER] [SLIDES]
- W. Zhang, K. Chun, C.H. Kim, "Variation Aware Performance Analysis of Gain Cell Embedded DRAMs", International Symposium on Low Power Electronics and Design (ISLPED), August 2010 [PAPER] [SLIDES]
- [Invited] K. Chun, P. Jain, and C.H. Kim, "Logic-Compatible Embedded DRAM Design for Memory Intensive Low Power Systems", International Symposium on Circuits and Systems (ISCAS), May 2010
- [Invited] J. Keane, X. Wang, D. Persaud, and C.H. Kim, "A High Resolution On-Chip Beat Frequency Detection System for Measuring BTI, HCI, and TDDB ", International Conference on Integrated Circuit Design and Technology (ICICDT), May 2010
- [Invited] C.H. Kim, "Silicon Odometers: On-Chip Test Structures for Accurately Monitoring Circuit Degradation Due to HCI, BTI, and TDDB", VLSI Test Symposium (VTS), April 2010
- Y. Xia, W. Zhang, M. Ha, J. Cho, M. Renn, C.H. Kim, C.D. Frisbie, "Printed Sub-2 V Gel-Electrolyte-Gated Polymer Transistors and Circuits", Advanced Functional Materials, 2010 [PAPER]
- [Invited] J. Keane, X. Wang, D. Persaud, and C.H. Kim, "An All-in-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB", IEEE Journal of Solid-State Circuits (JSSC), 2010 [PAPER]
- J. Keane, T. Kim, and C.H. Kim, "An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation", IEEE Trans. on VLSI Systems, June 2010 [PAPER]
- [Invited] J. Keane, X. Wang, T. Kim, and C.H. Kim, "On-Chip Reliability Monitors for Measuring Circuit Degradation", Microelectronics Reliability Journal, Aug. 2010 [PAPER]
- M. Ha, X. Yu, A. Green, W. Zhang, M. Renn, C.H. Kim, M. Hersam, C.D. Frisbie, "Printed, Sub-3 V Digital Circuits on Plastic from Aqueous Carbon Nanotube Inks", ACS Nano, 2010 [PAPER]
- P. Jain, P. Zhou, C.H. Kim, and S.S. Sapatnekar, "Thermal and Power Delivery Challenges in 3D ICs", Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Y. Xie, J. Cong, and S. Sapatnekar, eds., Springer, Boston, MA, 2010
- [Featured in IEEE Spectrum Magazine, invited to JSSC special issue] J. Keane, D. Persaud, and C.H. Kim, "An All-in-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB", VLSI Circuits Symposium, June 2009 [PAPER][SLIDES] [Online article]
- [ISLPED International Low Power Design Contest Winner] K. Chun, P. Jain, J. Lee, C.H. Kim, "A Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell, Regulated Bit-line Write Scheme and PVT-tracking Read Reference Bias", VLSI Circuits Symposium, June 2009 [PAPER] [SLIDES]
- D. Jiao, J. Gu, C.H. Kim, "Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise", Custom Integrated Circuits Conference (CICC), Sep. 2009 [PAPER] [SLIDES]
- T. Kim, W. Zhang, C.H. Kim, "An SRAM Reliability Test Macro for Fully-Automated Statistical Measurements of VminDegradation", Custom Integrated Circuits Conference (CICC), Sep. 2009 [PAPER] [SLIDES]
- [Best in Session Award] J. Keane, D. Persaud, and C.H. Kim, "An All-in-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB", TECHCON, Sep. 2009
- [Invited] C. Kim, "On-Chip Reliability Monitors: Circuit Ideas, Measurements, and Limitations", IEEE/ACM Workshop on Variability Modeling and Characterization, Nov. 2009
- S.V. Kumar, C.H. Kim, and S. Sapatnekar, "Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits", Asia-South Pacific Design Automation Conference (ASP-DAC), Jan. 2009 [PAPER]
- T. Kim, J. Liu, and C.H. Kim, "A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits (JSSC), 2009 [PAPER]
- J. Gu, H. Eom, and C.H. Kim, "On-chip Supply Noise Regulation Using a Low Power Digital Switched Decoupling Capacitor Circuit", IEEE Journal of Solid-State Circuits (JSSC), 2009 [PAPER]
- J. Gu, R. Harjani, and C.H. Kim, "Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs", IEEE Trans. on VLSI Systems, Feb. 2009 [PAPER]
- S.V. Kumar, C.H. Kim, and S.S. Sapatnekar, "A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability", IEEE Trans. on Device and Materials Reliability, Dec. 2009 [PAPER]
- [DAC/ISSCC Design Contest Winner] J. Keane, S. Venkatraman, P. Butzen, and C.H. Kim, "An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization", Custom Integrated Circuits Conference (CICC), Sep. 2008 [PAPER] [SLIDES]
- [AMD/CICC student scholarship award] T. Kim, J. Liu, and C.H. Kim, "A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode", Custom Integrated Circuits Conference (CICC), Sep. 2008 [PAPER][SLIDES]
- P. Jain, T. Kim, J. Keane, and C.H. Kim, "A Multi-Story Power Delivery Technique for 3D Integrated Circuits", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2008 [PAPER] [SLIDES]
- D. Jiao, J. Gu, P. Jain, and C.H. Kim, "Enhancing Benefitical Jitter Using Phase-Shifted Clock Distribution", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2008 [PAPER] [SLIDES]
- J. Keane, T. Kim, and C.H. Kim, "Silicon Odometers: On-Chip Test Structures for Monitoring Reliability Mechanisms and Sources of Variation", Workshop on Test Structure Design for Variability Characterization, Nov. 2008 [PAPER]
- [Invited] T. Kim, J. Liu, J. Keane, and C.H. Kim, "Circuit Techniques for Ultra-Low Power Subthreshold SRAMs", International Symposium on Circuits and Systems (ISCAS), June 2008 [PAPER]
- [Invited] T. Kim, R. Persaud, and C.H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits (JSSC), Apr. 2008 [PAPER]
- J. Kil, J. Gu, and C. Kim, "A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting", IEEE Trans. on VLSI Systems, Apr. 2008 [PAPER]
- J. Keane, H. Eom, T. Kim, S. Sapatnekar, and C. Kim, "Stack Sizing for Optimal Current Drivability in Subthreshold Circuits", IEEE Trans. on VLSI Systems, May 2008 [PAPER]
- T. Kim, J. Liu, J. Keane, and C. Kim, "A 0.2V, 480kb Subthreshold SRAM with 1k Cells per Bitline for Ultra-Low Voltage Computing", IEEE Journal of Solid-State Circuits (JSSC), Feb. 2008 [PAPER]
- S. Kumar, C. Kim, and S. Sapatnekar, "Body Bias Voltage Computations for Process and Temperature Compensation", IEEE Trans. on VLSI Systems, Mar. 2008 [PAPER]
- J. Gu, J. Keane, S. Sapatnekar, and C. Kim, "Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property", IEEE Trans. on VLSI Systems, Feb. 2007 [PAPER]
- J. Gu, J. Keane, and C. Kim, "Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity", IEEE Trans. on VLSI Systems, Dec. 2008 [PAPER]
- T. Kim, J. Liu, J. Keane, and C.H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", International Solid-State Circuits Conference (ISSCC), Feb 2007 [PAPER] [SLIDES]
- [DAC/ISSCC Design Contest Winner, invited to JSSC special issue] T. Kim, R. Persaud, and C.H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", VLSI Circuits Symposium, June 2007 [PAPER] [SLIDES]
- J. Gu, H. Eom, and C.H. Kim, "A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping", VLSI Circuits Symposium, June 2007 [PAPER] [SLIDES]
- [Best paper candidate, top 2% out of 713 submissions] J. Gu, S. Sapatnekar, and C.H. Kim, "Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift", Design Automation Conference, June 2007 [PAPER] [SLIDES]
- S. Kumar, C.H. Kim, and S. Sapatnekar, "NBTI-Aware Synthesis of Digital Circuits", Design Automation Conference, June 2007 [PAPER] [SLIDES]
- T. Kim, J. Liu, and C.H. Kim, "An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement", Custom Integrated Circuits Conference, Oct 2007 [PAPER] [SLIDES]
- J. Keane, T. Kim, and C.H. Kim, "An On-chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation", International Symposium on Low Power Electronics and Design (ISLPED), Aug 2007 [PAPER] [SLIDES]
- J. Gu, H. Eom, and C.H. Kim, "Sleep Transistor Sizing and Control for Resonant Supply Noise Damping", International Symposium on Low Power Electronics and Design (ISLPED), Aug 2007 [PAPER] [SLIDES]
- J. Keane, A. Drake, AJ KleinOsowski, E. Cannon, F. Gebara, and C.H. Kim, "Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit", NASA Symposium on VLSI Design, June 2007 [PAPER]
- P. Butzen, A. Reis, C.H. Kim, R. Ribas, "Modeling and Estimating Leakage Current in Series-Parallel CMOS Networks", Great Lakes Symposium on VLSI (GLSVLSI), Mar 2007
- P. Butzen, A. Reis, C.H. Kim, R. Ribas, "Modeling Subthreshold Leakage Current in General Transistor Networks", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), May 2007
- P. Butzen, A. Reis, C.H. Kim, R. Ribas, "Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates", International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep 2007
- T. Kim, H. Eom, J. Keane, and C. Kim, "Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design", IEEE Trans. on VLSI Systems, July 2007 [PAPER]
DESIGN CONTEST AND BEST PAPER AWARDS
- 2019 Women in Hardware and Systems Security, Best Poster Award (2nd place out of 32 posters), M. Liu, K. Parhi, and C.H. Kim, “A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function”
- 2017 ISLPED Best Paper Award, M. Liu, C. Zhou, K. Parhi, and C.H. Kim, “A Data Remanence based Approach to Generate 100% Stable Bits from an SRAM Physical Unclonable Function”
- 2016 ISLPED Best Paper Award, C. Zhou, S. Satapathy, Y. Lao, K. Parhi, and C.H. Kim, “Soft Response Generation and Thresholding Strategies for Linear and Feedforward MUX based PUFs”
- 2013 ISLPED International Low Power Design Contest Award: B. Kim, W. Xu, C.H. Kim, "An Adaptive PLL in 32nm SOI for Optimal Processor Power and Performance under Resonant Supply Noise"
- 2012 ISLPED International Low Power Design Contest Award: S. Song, K.C. Chun, C.H. Kim, "An Embedded Flash Memory in a Generic 65nm Logic Process for Zero-Standby-Power System-on-Chip Applications"
- 2009 SRC Techcon Best in Session Award: J. Keane, D. Persaud, and C.H. Kim, "An All-in-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB"
- 2009 ISLPED International Low Power Design Contest Award: K. Chun, P. Jain, C.H. Kim, "A 0.9V, 65nm Logic-compatible Embedded DRAM with >1ms Data Retention Time and 53% Less Static Power than a Power-Gated SRAM"
- 2009 DAC/ISSCC Design Contest Award: J. Keane, S. Venkatraman, P. Butzen, and C.H. Kim, "A Fully-Automated Process Characterization Macro for Gate Dielectric Breakdown"
- 2008 AMD/CICC Student Scholarship Award: T. Kim, J. Liu, and C.H. Kim, "A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode"
- 2008 DAC/ISSCC Design Contest Award: T. Kim, R. Persaud, and C.H. Kim, "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits"
- 2008 Samsung Humantech Thesis Competition Bronze Medal: T. Kim, J. Liu, and C.H. Kim, "A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode"
- 2005 ISLPED International Low Power Design Contest Award: C.H. Kim, J. Kim, I. Chang, and K. Roy, "PVT_AwareLeakage Reduction for On-Die Caches with Improved Read Stability"